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146 lines
6.0 KiB
146 lines
6.0 KiB
/************************************************************************************
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* configs/px4fmu/include/board.h
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* include/arch/board/board.h
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*
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* Copyright (C) 2009 Gregory Nutt. All rights reserved.
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* Author: Gregory Nutt <gnutt@nuttx.org>
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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*
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in
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* the documentation and/or other materials provided with the
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* distribution.
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* 3. Neither the name NuttX nor the names of its contributors may be
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* used to endorse or promote products derived from this software
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* without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
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* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
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* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
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* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
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* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
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* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
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* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
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* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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* POSSIBILITY OF SUCH DAMAGE.
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*
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************************************************************************************/
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#include "board_dma_map.h"
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#ifndef __ARCH_BOARD_BOARD_H
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#define __ARCH_BOARD_BOARD_H
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#include <nuttx/config.h>
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#ifndef __ASSEMBLY__
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# include <stdint.h>
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#endif
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#include <stm32.h>
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#define STM32_BOARD_XTAL 16000000ul
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#define STM32_HSI_FREQUENCY 16000000ul
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#define STM32_LSI_FREQUENCY 32000
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#define STM32_HSE_FREQUENCY STM32_BOARD_XTAL
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#define STM32_BOARD_USEHSE 1
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#define STM32_LSE_FREQUENCY 0
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/* PLL source is HSE
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* PLL_VCO = (STM32_HSE_FREQUENCY / PLLM) * PLLN
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* = (16'000'000 / 16) * 384
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* = 384'000'000
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* SYSCLK = PLL_VCO / PLLP
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* = 384'000'000 / 4 = 96,000,000
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*/
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/* Main PLL Configuration */
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#define STM32_PLLCFG_PLLM RCC_PLLCFG_PLLM(16)
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#define STM32_PLLCFG_PLLN RCC_PLLCFG_PLLN(384)
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#define STM32_PLLCFG_PLLP RCC_PLLCFG_PLLP_4
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#define STM32_PLLCFG_PLLQ RCC_PLLCFG_PLLQ(8)
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#define STM32_PLLCFG_PLLR RCC_PLLCFG_PLLR(2)
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#define STM32_RCC_PLLI2SCFGR_PLLI2SM RCC_PLLI2SCFGR_PLLI2SM(16)
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#define STM32_RCC_PLLI2SCFGR_PLLI2SN RCC_PLLI2SCFGR_PLLI2SN(192)
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#define STM32_RCC_PLLI2SCFGR_PLLI2SQ RCC_PLLI2SCFGR_PLLI2SQ(2)
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#define STM32_RCC_PLLI2SCFGR_PLLI2SR RCC_PLLI2SCFGR_PLLI2SR(2)
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#define STM32_RCC_PLLI2SCFGR_PLLI2SSRC RCC_PLLI2SCFGR_PLLI2SSRC(0) /* HSE or HSI depending on PLLSRC of PLLCFGR*/
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#define STM32_RCC_DCKCFGR2_CK48MSEL RCC_DCKCFGR2_CK48MSEL_PLL
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#define STM32_RCC_DCKCFGR2_FMPI2C1SEL RCC_DCKCFGR2_FMPI2C1SEL_APB
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#define STM32_RCC_DCKCFGR2_SDIOSEL RCC_DCKCFGR2_SDIOSEL_48MHZ
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#define STM32_SYSCLK_FREQUENCY 96000000ul
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/* AHB clock (HCLK) is SYSCLK (96MHz) */
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#define STM32_RCC_CFGR_HPRE RCC_CFGR_HPRE_SYSCLK /* HCLK = SYSCLK / 1 */
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#define STM32_HCLK_FREQUENCY STM32_SYSCLK_FREQUENCY
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#define STM32_BOARD_HCLK STM32_HCLK_FREQUENCY /* Same as above, to satisfy compiler */
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/* APB1 clock (PCLK1) is HCLK/2 (48MHz) */
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#define STM32_RCC_CFGR_PPRE1 RCC_CFGR_PPRE1_HCLKd2 /* PCLK1 = HCLK / 2 */
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#define STM32_PCLK1_FREQUENCY (STM32_HCLK_FREQUENCY/2)
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/* Timers driven from APB1 will be twice PCLK1 (see page 112 of reference manual) */
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#define STM32_APB1_TIM2_CLKIN (2*STM32_PCLK1_FREQUENCY)
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#define STM32_APB1_TIM3_CLKIN (2*STM32_PCLK1_FREQUENCY)
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#define STM32_APB1_TIM4_CLKIN (2*STM32_PCLK1_FREQUENCY)
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#define STM32_APB1_TIM5_CLKIN (2*STM32_PCLK1_FREQUENCY)
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#define STM32_APB1_TIM12_CLKIN (2*STM32_PCLK1_FREQUENCY)
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#define STM32_APB1_TIM13_CLKIN (2*STM32_PCLK1_FREQUENCY)
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#define STM32_APB1_TIM14_CLKIN (2*STM32_PCLK1_FREQUENCY)
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/* APB2 clock (PCLK2) is HCLK (96MHz) */
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#define STM32_RCC_CFGR_PPRE2 RCC_CFGR_PPRE2_HCLK /* PCLK2 = HCLK */
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#define STM32_PCLK2_FREQUENCY (STM32_HCLK_FREQUENCY)
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/* Timers driven from APB2 will be PCLK2 since no prescale division */
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#define STM32_APB2_TIM1_CLKIN (STM32_PCLK2_FREQUENCY)
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#define STM32_APB2_TIM8_CLKIN (STM32_PCLK2_FREQUENCY)
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#define STM32_APB2_TIM9_CLKIN (STM32_PCLK2_FREQUENCY)
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#define STM32_APB2_TIM10_CLKIN (STM32_PCLK2_FREQUENCY)
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#define STM32_APB2_TIM11_CLKIN (STM32_PCLK2_FREQUENCY)
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/* Timer Frequencies, if APBx is set to 1, frequency is same to APBx otherwise frequency is 2xAPBx. */
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#define BOARD_TIM2_FREQUENCY (2 * STM32_PCLK1_FREQUENCY)
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#define BOARD_TIM3_FREQUENCY (2 * STM32_PCLK1_FREQUENCY)
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#define BOARD_TIM4_FREQUENCY (2 * STM32_PCLK1_FREQUENCY)
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#define BOARD_TIM5_FREQUENCY (2 * STM32_PCLK1_FREQUENCY)
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#define BOARD_TIM6_FREQUENCY (2 * STM32_PCLK1_FREQUENCY)
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#define BOARD_TIM7_FREQUENCY (2 * STM32_PCLK1_FREQUENCY)
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#define BOARD_TIM8_FREQUENCY (2 * STM32_PCLK2_FREQUENCY)
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/* Alternate function pin selections ************************************************/
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/* UARTs */
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#define GPIO_USART1_RX GPIO_USART1_RX_1
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#define GPIO_USART1_TX GPIO_USART1_TX_1
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/* CAN */
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#define GPIO_CAN1_RX GPIO_CAN1_RX_2 /* PB8 */
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#define GPIO_CAN1_TX GPIO_CAN1_TX_2 /* PB9 */
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/* SPI */
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#define GPIO_SPI1_MISO GPIO_SPI1_MISO_1 /* PA6 */
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#define GPIO_SPI1_MOSI GPIO_SPI1_MOSI_1 /* PA7 */
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#define GPIO_SPI1_SCK GPIO_SPI1_SCK_1 /* PA5 */
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#define GPIO_SPI2_MISO GPIO_SPI2_MISO_1 /* PB14 */
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#define GPIO_SPI2_MOSI GPIO_SPI2_MOSI_1 /* PB15 */
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#define GPIO_SPI2_SCK GPIO_SPI2_SCK_2 /* PB13 */
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#define GPIO_SPI3_MISO GPIO_SPI3_MISO_1 /* PB4 */
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#define GPIO_SPI3_MOSI GPIO_SPI3_MOSI_1 /* PB5 */
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#define GPIO_SPI3_SCK GPIO_SPI3_SCK_1 /* PB3 */
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#endif /* __ARCH_BOARD_BOARD_H */
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