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126 lines
4.4 KiB
126 lines
4.4 KiB
/****************************************************************************
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*
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* Copyright (c) 2020 PX4 Development Team. All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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*
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in
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* the documentation and/or other materials provided with the
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* distribution.
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* 3. Neither the name PX4 nor the names of its contributors may be
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* used to endorse or promote products derived from this software
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* without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
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* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
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* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
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* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
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* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
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* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
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* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
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* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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* POSSIBILITY OF SUCH DAMAGE.
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*
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****************************************************************************/
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#pragma once
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/*
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FDCAN2 => no DMA, but dedicated message RAM
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ETH => has its own DMA engine
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I2C => has its own DMA engine
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The rest are general DMA engines:
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MDMA (D1): not supported by NuttX
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DMA1 (D2): 8 streams, mapped to DMAMUX1 requests 0-7
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DMA2 (D2): 8 streams, mapped to DMAMUX1 requests 8-15
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BDMA (D3): 8 streams, mapped to DMAMUX2 requests 0-7
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I2C1_RX => DMAMUX1:33 (EXT)
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I2C1_TX => DMAMUX1:34 (EXT)
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I2C4_RX => DMAMUX2:29 (BARO + MAG + EEPROM)
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I2C4_TX => DMAMUX2:30 (BARO + MAG + EEPROM)
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SPI3_RX => DMAMUX1:61 (IMU3 BMI088)
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SPI3_TX => DMAMUX1:62 (IMU3 BMI088)
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SPI4_RX => DMAMUX1:83 (FRAM)
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SPI4_TX => DMAMUX1:84 (FRAM)
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UART4_RX => DMAMUX1:63 (NSH DEBUG)
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UART4_TX => DMAMUX1:64 (NSH DEBUG)
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UART7_RX => DMAMUX1:79 (SBUS INPUT)
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UART7_RX => DMAMUX1:79 (ESC RX)
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UART8_RX => DMAMUX1:81 (GPS)
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UART8_TX => DMAMUX1:82 (GPS)
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USART3_RX => DMAMUX1:45 (EXTRAS)
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USART3_TX => DMAMUX1:46 (EXTRAS)
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USART1_RX => DMAMUX1:41 (MAVLINK)
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USART1_TX => DMAMUX1:42 (MAVLINK)
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USART2_RX => DMAMUX1:43 (NSH IMX)
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USART2_TX => DMAMUX1:44 (NSH IMX)
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(TIM1_CH1 => DMAMUX1:11)
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(TIM1_CH2 => DMAMUX1:12)
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(TIM1_CH3 => DMAMUX1:13)
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(TIM1_CH4 => DMAMUX1:14)
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TIM1_UP => DMAMUX1:15 (PWM)
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(TIM3_CH1 => DMAMUX1:23)
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(TIM3_CH2 => DMAMUX1:24)
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(TIM3_CH3 => DMAMUX1:25)
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(TIM3_CH4 => DMAMUX1:26)
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TIM3_UP => DMAMUX1:27 (PWM)
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TIM8_CH2 => DMAMUX1:48 (PPM INPUT)
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(TIM8_UP => DMAMUX1:51)
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*/
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// DMAMUX1 Using at most 8 Channels on DMA1 -------- Assigned
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// V
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#define DMAMAP_USART1_RX DMAMAP_DMA12_USART1RX_0 /* 1 TELEM1 (MAVLINK) */
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#define DMAMAP_USART1_TX DMAMAP_DMA12_USART1TX_0 /* 2 TELEM1 (MAVLINK) */
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#define DMAMAP_UART8_RX DMAMAP_DMA12_UART8RX_0 /* 3 GPS1 */
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#define DMAMAP_UART8_TX DMAMAP_DMA12_UART8TX_0 /* 4 GPS1 */
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#define DMAMAP_USART2_TX DMAMAP_DMA12_USART2TX_0 /* 5 NSH IMX TX */
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#define DMAMAP_UART4_TX DMAMAP_DMA12_UART4TX_0 /* 6 NSH DBG TX */
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// Assigned in timer_config.cpp
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// Timer 1 /* 7 TIM1UP */
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// Timer 3 /* 8 TIM3UP */
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// DMAMUX2 Using at most 8 Channels on DMA2 -------- Assigned
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// V
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#define DMAMAP_SPI3_RX DMAMAP_DMA12_SPI3RX_1 /* 1 BMI088 */
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#define DMAMAP_SPI3_TX DMAMAP_DMA12_SPI3TX_1 /* 2 BMI088 */
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#define DMAMAP_SPI4_RX DMAMAP_DMA12_SPI4RX_1 /* 3 FRAM */
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#define DMAMAP_SPI4_TX DMAMAP_DMA12_SPI4TX_1 /* 4 FRAM */
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#define DMAMAP_USART3_RX DMAMAP_DMA12_USART3RX_1 /* 5 TELEM2 */
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#define DMAMAP_USART3_TX DMAMAP_DMA12_USART3TX_1 /* 6 TELEM2 */
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#define DMAMAP_UART5_RX DMAMAP_DMA12_UART5RX_1 /* 7 SBUS IN */
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#define DMAMAP_UART7_RX DMAMAP_DMA12_UART7RX_1 /* 8 ESC IN */
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